Complex digital systems can be built with the use of only a few simple logic circuits or gates, such as inverters, NAND gates and NOR gates. These logic gates are typically implemented as semiconductor integrated circuits (ICs). Each logic circuit or gate is similar in outline and geometry and consists of one or more output drivers driving one or more connected loads. The logic gate can be made using one of several conventional semiconductor processes and/or corresponding devices, such as a bipolar junction transistor, a junction field-effect transistor (JFET), or a metal oxide semiconductor field effect transistor (MOSFET). The driver of a logic gate is usually defined by variety of circuit specification and system parameters. Logic ICs may be grouped into families based on driver specifications. Consequently, bipolar ICs, JFET ICs, and MOS ICs logic families are well known by the driver specifications. The MOSFET is a widely used device for implementing logic gates. MOSFET ICs consist almost entirely of active MOSFET devices which are small, high input impedance, low power consumption and inherently isolated devices. The MOSFET manufacturing process has been refined to produce high yield ICs even at the very large-scale integration (VLSI) levels.
The MOSFETs have a drain to source current ID versus voltage VDS plot for enhancement-mode MOS transistors. Below saturation or pinch-off, the device operates as a non linear voltage controlled resistor in an operating region often called the ohmic region of the MOSFET. Beyond saturation the MOSFET behaves as a voltage controlled current source. An enhancement-mode MOSFET transistor remains in saturation when its gate is shorted to its drain so long the gate-source voltage exceeds the threshold voltage VT of the MOSFET. The ID vs. VDS characteristics make the enhancement-mode MOSFET well suited for implementation as a current mirror load.
The conventional configuration the MOSFET current mirror load consists of a first current enhancement mode MOSFET and a second enhancement-mode MOSFETs having the two gate inputs connected together so that the current in second mirror MOSFET mirrors the current in the first current MOSFET. The first current MOSFET is series connected to a current source CS having a reference current I. Consequently, this same current I is conducted through second mirror MOSFET providing a current mirror load having a load current. The current source is typically implemented by a resistor.
The first current MOSFET which is series connected with the current source and operates in saturation when the VDS exceeds the threshold voltage VT as a result of the gate connected to the drain. When the first current MOSFET and the second mirror MOSFET are identical devices with identical geometries, then the second mirror MOSFET will also be in saturation as long as VDS is greater than or equal to VT. Under these circumstances, the drain current of the second mirror MOSFET is identical to the drain current of the first current MOSFET which is equal to the current I of the current source. The drain current of the second mirror MOSFET is considered a load current IL and is constant as long as the second mirror MOSFET remains in saturation. The current mirror is frequently used in ICs to reproduce current at one location to one or more other locations within a large interconnected integrated circuit. The current of first current MOSFET may be mirrored into several other second mirror MOSFETs. One current source and a respective current MOSFET may be connected to a plurality of mirror MOSFETs providing a respective plurality current mirror loads each having the current IL.
U.S. Pat. No. 4,670,671 entitled High Speed Comparator Having Controlled Hysteresis, discloses a CMOS analog circuit having resistive network comprising a resistive current source and a resistive current transistor for providing a bias voltage connected to two current transistors designated as current sources for an input differential stage and a feedback differential stage. The resistive network has an external control input VON for controlling the current on and off through the mirror transistors. Hence, the current mirror has a controlled current source connected to current transistor connected to a mirror transistors. The current of the mirror transistors that can be externally turned off and on. CMOS analog circuits have used CMOS current mirrors comprising a current source conducting the current I through a current transistor coupled to a mirror transistor conducting the same current as the current transistor and providing a high impedance current mirror load which when integrated into analog amplifiers, provide the amplifier with high gain.
The current mirror continuously conducts currents and as such continuously dissipates power during operation use. Current mirror loads have not been used in conventional CMOS logic circuits which do not dissipate power when in a stable logic state. Constant current loads are not used in logic circuit because high continuous power dissipation results when using constant current loads. Logic CMOS circuits use switching transistors which conduct current and dissipate power during transitions between one logic state to another. Conventional CMOS logic circuit are dynamic, in that, the CMOS logic circuits dissipate power only while charging or discharging the internal transistors and load capacitances as the output signal changes from one state to another state. During logic transitions when power dissipation is dynamic, the power dissipation disadvantageously increases as the frequency of operation increase. With increasing speeds of VLSI operation, dynamic CMOS logic circuits suffer from increased power dissipation. The use of a constant current load at very low level of current may seem to be an advantageous alternative of providing a current load for high impedance driver loads providing rapid switching. However, at very low current, variations of the threshold voltage of the transistors dramatically affects the constant current which may result in the failure of the logic circuit to maintain the proper output logic state.
Logic circuits provide output signal levels which correspond to digital bits one or zero. The ability to distinguish voltage levels determines when a signal is a binary zero or a binary one, and is essential for proper logic circuit operation. It is desirable to provide output signals which have output signal levels that do not vary over operating conditions. It is further desirable to provide low power operating conditions.
In CMOS logic circuits, the output voltage levels are a function of the threshold voltage VT of the FET transistors. An, undesirable feature of MOSFETs is that when they are exposed to radiation, the threshold voltage VT of the devices shifts. This shift in VT affects the operation of MOS ICs, resulting in degraded circuit performance. It is well known that when NMOS devices undergo radiation, the VT tends to become less positive, while the VT of irradiated PMOS devices tends to become more negative. At some point of accumulated exposure to radiation, MOSFET devices would fail. Radiation protection options are disadvantageously limited when producing radiation hardened systems. Often, systems use radiation hardened processing methods and error-correction software to recover from failing devices affected by radiation.
The threshold voltage VT varies during operation when radiated by an external source, such as the sun. Device current levels may change due to the change in the threshold voltage. As the accumulated radiation increases, the threshold voltage of PMOS transistors increases as the threshold voltage of NMOS transistors decreases, affecting current and slowing the operation of the CMOS logic circuit through reduced capacitive charge currents. The affects of changing threshold voltages and resulting changes in operating current have rendered low current low power dissipating current mirror loads ineffective or undesirable in logic circuits. CMOS logic circuits disadvantageously suffer from varying output voltage signal levels and current levels when radiated, and have rendered ineffective the use very low current mirror loads for fast low power operation. These and other disadvantages are solved or reduced using the present invention.